Five-level Guest Page Table Support in AMD IOMMU on Linux 6.4

In the year 2021, AMD initiated the process of developing Linux kernel support for 5-level paging support with the intention of incorporating it into their future processors. They were able to accomplish this by expanding upon the 5-level page table kernel support that had been developed previously by Intel. After that, AMD updated the Linux 5.15 kernel to include support for a 5-level page table within KVM SVM. Since the time of their introduction, AMD has made its central processing units (CPUs) available in the form of 4th Generation EPYC “Genoa” processors. These processors are able to support 5-level page tables.

Support for 5-level guest page tables has been added to the AMD IOMMU driver, which was a feature that was absent in the past but can now be found in the updated version. Support for 5-level page tables is necessary in order to considerably increase the amount of virtual and physical address space that is accessible. This is in comparison to 4-level page tables, which do not have this support. When 5 level paging is being utilized, there is support for addressing physical memory addresses up to 4 piB in size. This is entirely feasible. One and only disadvantage of having an additional page table level is the necessity of walking further to reach each page table.

The AMD IOMMU driver (amd_iommu), which is planned to be included in the 6.4 version of the Linux kernel that is currently being developed, is going to receive support for 5-level guest page tables. This support will be implemented in the next weeks. If the processor and IOMMU are able to support 5-level page tables, the Linux 6.4 kernel will activate them. If they cannot be supported, the kernel will revert to the 4-level page tables that are currently being used. The NUMA-awareness capability has also been added to the memory allocations that are handled by the AMD IOMMU driver for Linux 6.4.