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TSMC may lower prices for 3nm chips in order to attract AMD and Nvidia


Although the N3 (3nm-class) family of manufacturing methods from TSMC offers a lot of advantages in terms of performance and power consumption, widespread adoption of these technologies is hampered by the extremely high pricing of the foundry’s initial N3 node. At this moment, any public quotes and pricing for TSMC’s N3 should be considered to be rumours; nonetheless, it is anticipated that TSMC’s production costs on its N3E process will be lower than those on its initial N3; this prediction is based on the fact that the N3E process is more efficient.

How much the corporation would charge for production on other N3-class nodes, such as N3P, N3S, and N3X, is something that has not been determined as of yet. Bringing down the costs of manufacturing at 3nm will entice more customers to purchase at these nodes, but this is not going to be something that happens quickly. Apple is said to be the only firm to employ TSMC’s original N3 manufacturing technology, which is sometimes referred to as N3B. This is due to the fact that Apple is the foundry’s largest client ready to adopt leading-edge nodes ahead of other companies.

It has been speculated that TSMC may be charging as much as $20,000 per N3 wafer, which would be an increase from the previous price of $16,000 per N5 wafer. Although the accuracy of such estimates is contingent on a variety of factors, the most important takeaway is that the cost of manufacturing chips continues to rise. Companies like AMD, Broadcom, MediaTek, Nvidia, and Qualcomm are seeing their revenues decline as a direct result of rising prices. As a result, chip developers are reevaluating the methods by which they produce innovative designs and make use of cutting-edge nodes.

According to a piece written by Szeho Ng, an analyst at China Renaissance, “We believe the meaningful [N3] ramp-up will be in 2H 2023 when the optimised version, N3E, would be ready.” [Citation needed] “According to our analysis, the company’s major clients in the high-performance computing market (i.e. AMD and Intel), the smartphone market (i.e. QCOM and MTK), and the application-specific integrated circuit market (i.e. MRVL, AVGO, and GUC) will most likely remain in the N4/5 class and will select N3E as their first foray into the N3 class. In the meantime, we think that the adoption of the baseline N3 (also known as N3B) will primarily be limited to Apple products.”

According to recent reports, TSMC is contemplating decreasing the prices it charges for these nodes in an effort to encourage its business partners to use the N3-class process technology it has developed. In specifically, the N3E process that TSMC uses utilises EUV for a maximum of 19 layers, but because it has a somewhat reduced level of complexity in terms of its production, it is more cost effective to use. The prices of N3E manufacture at TSMC could be lowered without having an adverse effect on profitability. When it comes to SRAM cell scaling, N3E offers no advantages over N5, which results in bigger die sizes in comparison to those produced on N3/N3B.

Nvidia is anticipated to incorporate N3 for its next-generation Blackwell architecture-based GPUs, which are scheduled to debut around the same date as AMD’s public announcement that it planned to employ a N3 node for parts of the Zen 5-based architectures that it intends to release in 2024. Because of the high costs associated with adopting N3-class nodes, it is anticipated that their use will be restricted to a select number of devices; hence, a reduction in prices will most likely cause chip designers to reevaluate their adoption strategy.